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1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)
CORDIC Architectures with Parallel Compensation of the Scale Factor
Strasbourg, France
July 24-July 26
ISBN: 0-8186-7109-2
ASCII Text
x 
 
J. Villalba, J.A. Hidalgo, E.L. Zapata, E. Antelo, J.D. Bruguera, "CORDIC Architectures with Parallel Compensation of the Scale Factor," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 258, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995.
 
 
BibTex
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@article{ 10.1109/ASAP.1995.522930,
author = {J. Villalba and J.A. Hidalgo and E.L. Zapata and E. Antelo and J.D. Bruguera},
title = {CORDIC Architectures with Parallel Compensation of the Scale Factor},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1995},
issn = {1063-6862},
pages = {258},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522930},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - CORDIC Architectures with Parallel Compensation of the Scale Factor
SN - 1063-6862
SP
EP
A1 - J. Villalba,
A1 - J.A. Hidalgo,
A1 - E.L. Zapata,
A1 - E. Antelo,
A1 - J.D. Bruguera,
PY - 1995
KW - CORDIC algorithm
KW - Scale Factor
KW - Redundant Arithmetic
KW - Parallel Architecture
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
J. Villalba, University of Malaga, SPAIN
J.A. Hidalgo, University of Malaga, SPAIN
E.L. Zapata, University of Malaga, SPAIN
E. Antelo, University of Santiago de Compostela, SPAIN
J.D. Bruguera, University of Santiago de Compostela, SPAIN
The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we will propose two algorithms and architectures in order to perform the compensation of the scale factor in parallel with the computation of the CORDIC iterations. This way it is not necessary to carry out the final multiplication or add scaling iterations in order to achieve the compensation. With the architectures we propose the dependence on n of the compensation of the scale factor disappears, and this considerably reduces the latency of the system. The architectures developed are optimized solutions for the different operating modes of the CORDIC both in conventional and in redundant arithmetic.
Index Terms:
CORDIC algorithm, Scale Factor, Redundant Arithmetic, Parallel Architecture
Citation:
J. Villalba, J.A. Hidalgo, E.L. Zapata, E. Antelo, J.D. Bruguera, "CORDIC Architectures with Parallel Compensation of the Scale Factor," asap, pp.258, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995
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