Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H.261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires the use of special purpose architectures to obtain real-time performance. In this paper we propose an approach to the parallel implementation of the Full Search Block Matching Algorithm which is suitable for implementation on massively parallel architectures ranging from large scale SIMD computers to dedicated processor arrays realized in ASICs. While the first alternative can be used for the implementation of high performance coders the second alternative is particularly attractive for low cost video compression devices. This paper describes the approach proposed for the parallel implementation of the Full Search Block Matching Algorithm and the implementation of such an approach in an ASIC.