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1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)
The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs
Strasbourg, France
July 24-July 26
ISBN: 0-8186-7109-2
ASCII Text
x 
 
D.W. Brown, F.M.F. Gaston, "The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 141, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/ASAP.1995.522917,
author = {D.W. Brown and F.M.F. Gaston},
title = {The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {1995},
issn = {1063-6862},
pages = {141},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522917},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs
SN - 1063-6862
SP
EP
A1 - D.W. Brown,
A1 - F.M.F. Gaston,
PY - 1995
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
D.W. Brown, The Queen's University of Belfast
F.M.F. Gaston, The Queen's University of Belfast
Hierarchical Signal Flow Graphs (HSFGs) are used to illustrate the computations and the data flow required for the block regularised parameter estimation algorithm. This algorithm protects the parameter estimation from numerical difficulties associated with insufficiently exciting data, or where the behaviour of the underlying model is unknown. Hierarchical signal flow graphs (HSFG's) aid the user's understanding of the algorithm as they clearly show how the algorithm differs from exponentially weighted recursive least squares, but also allow the user to develop fast efficient parallel algorithms easily and effectively, as demonstrated in the paper.
Citation:
D.W. Brown, F.M.F. Gaston, "The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs," asap, pp.141, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995
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