The VLSI design and implementation of the array processors of a multilayer vision system architecture

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by B. Saha Articles by J.S. Mertoguno Articles by N.G. Bourbakis

1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)

Strasbourg, France

July 24-July 26

ISBN: 0-8186-7109-2

	ASCII Text	x
	B. Saha, J.S. Mertoguno, N.G. Bourbakis, "The VLSI design and implementation of the array processors of a multilayer vision system architecture," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 125, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995.

	BibTex	x
	@article{ 10.1109/ASAP.1995.522913, author = {B. Saha and J.S. Mertoguno and N.G. Bourbakis}, title = {The VLSI design and implementation of the array processors of a multilayer vision system architecture}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1995}, issn = {1063-6862}, pages = {125}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522913}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - The VLSI design and implementation of the array processors of a multilayer vision system architecture SN - 1063-6862 SP EP A1 - B. Saha, A1 - J.S. Mertoguno, A1 - N.G. Bourbakis, PY - 1995 KW - parallel processing; computer vision; VLSI; digital simulation; VLSI design; array processors; multilayer vision system architecture; KYDON vision system; multilayered image understanding system; timing simulation VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

B. Saha, Dept. of Electr. Eng., Binghamton Univ., NY, USA

J.S. Mertoguno, Dept. of Electr. Eng., Binghamton Univ., NY, USA

N.G. Bourbakis, Dept. of Electr. Eng., Binghamton Univ., NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522913

This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 image frames/sec.

Index Terms:

parallel processing; computer vision; VLSI; digital simulation; VLSI design; array processors; multilayer vision system architecture; KYDON vision system; multilayered image understanding system; timing simulation

Citation:

B. Saha, J.S. Mertoguno, N.G. Bourbakis, "The VLSI design and implementation of the array processors of a multilayer vision system architecture," asap, pp.125, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.