A simple array processor for binary prefix sums

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1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)

Strasbourg, France

July 24-July 26

ISBN: 0-8186-7109-2

	ASCII Text	x
	Rong Lin, S. Olariu, "A simple array processor for binary prefix sums," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 113, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995.

	BibTex	x
	@article{ 10.1109/ASAP.1995.522911, author = {Rong Lin and S. Olariu}, title = {A simple array processor for binary prefix sums}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {1995}, issn = {1063-6862}, pages = {113}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522911}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - A simple array processor for binary prefix sums SN - 1063-6862 SP EP A1 - Rong Lin, A1 - S. Olariu, PY - 1995 KW - parallel processing; computational complexity; VLSI; network routing; circuit CAD; array processor; binary prefix sums; binary sequence; operating system design; storage compaction; routing; processor assignment; special-purpose architecture VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Rong Lin, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA

S. Olariu, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522911

The task of computing the prefix sums of a binary sequence (BPS, for short) arises frequently in expression evaluation, data and storage compaction, routing, processor assignment, and operating system design. The main goal of this work is to propose an efficient special-purpose architecture for the BPS problem. Our design exploits a novel and elegant idea that allows us to considerably reduce the number of processors of the best-known design. The resulting design is simple and intuitive and scales easily to handle input sequences of various sizes.

Index Terms:

parallel processing; computational complexity; VLSI; network routing; circuit CAD; array processor; binary prefix sums; binary sequence; operating system design; storage compaction; routing; processor assignment; special-purpose architecture

Citation:

Rong Lin, S. Olariu, "A simple array processor for binary prefix sums," asap, pp.113, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995

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