loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)
A Scalable Halftoning Coprocessor Architecture
Strasbourg, France
July 24-July 26
ISBN: 0-8186-7109-2
Anders Kugler, Swiss Federal Institute of Technology
Roger-David Hersch, Swiss Federal Institute of Technology
Exact-angle superscreen dithering requires large dither tiles. Since storing precomputed screen elements for each intensity level would require too much memory, dithering must be executed on the fly at halftoning time. For this purpose, a dithering coprocessor is presented which generates halftoned images at high speed. The proposed hardware architecture is based on a pipelined and scalable design which speeds up halftoning by a factor of twenty compared with modern RISC software-based solutions. We describe the architecture of the coprocessor and show to what extent it can be scaled for improving performances. The proposed coprocessor could find applications in digital color copiers which need to print scanned color images at high speed.
Index Terms:
Halftoning, parallel dithering, coprocessor architecture
Citation:
Anders Kugler, Roger-David Hersch, "A Scalable Halftoning Coprocessor Architecture," asap, pp.76, 1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.