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2001 Conference on Advanced Research in VLSI (ARVLSI'01)
Width-Adaptive Data Word Architectures
Salt Lake City, Utah
March 14-March 16
ISBN: 0-7695-1038-8
ASCII Text
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Rajit Manohar, "Width-Adaptive Data Word Architectures," Advanced Research in VLSI, Conference on, pp. 112, 2001 Conference on Advanced Research in VLSI (ARVLSI'01), 2001.
 
 
BibTex
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@article{ 10.1109/ARVLSI.2001.915555,
author = {Rajit Manohar},
title = {Width-Adaptive Data Word Architectures},
journal ={Advanced Research in VLSI, Conference on},
volume = {0},
year = {2001},
isbn = {0-7695-1038-8},
pages = {112},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.2001.915555},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Advanced Research in VLSI, Conference on
TI - Width-Adaptive Data Word Architectures
SN - 0-7695-1038-8
SP
EP
A1 - Rajit Manohar,
PY - 2001
VL - 0
JA - Advanced Research in VLSI, Conference on
ER -
 
Rajit Manohar, Cornell University
We discuss number representations for width-adaptive data word architectures. The number representations are self-delimiting, permitting asynchronous implementations with dynamic width adaptivity and reduced energy-complexity. We describe how these architectures can be realized with asynchronous VLSI techniques, and show that they exhibit better energy and throughput characteristics than traditional asynchronous implementations. We study some of the tradeoffs in the design of this class of architectures.
Citation:
Rajit Manohar, "Width-Adaptive Data Word Architectures," arvlsi, pp.112, 2001 Conference on Advanced Research in VLSI (ARVLSI'01), 2001
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