As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are lowered can render some conventional logic circuit styles unusable. Furthermore, some low voltage circuits are not robust when faced with normal variations in threshold voltage. This paper examines the design considerations for logic and memory circuits in very low voltage CMOS, and compares simulated behavior with measurements of fabricated test circuits. These circuit examples were chosen because they illustrate the unique design challenges of low voltage CMOS.