20th Anniversary Conference on Advanced Research in VLSI Adaptive Circuits Using pFET Floating-Gate Devices Atlanta, Georgia March 21-March 24 ISBN: 0-7695-0056-0
In this paper, we describe our oating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add oating-gate charge by electron tunneling, and we remove floating- gate charge by hot-electron injection. With this floating-gate technology, we can not only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using the floating-gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we will discuss using floating-gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using floating-gate pFETs. The physics of adaptation start with floating-gate pFETs with continuous tunneling and injection currents. A single floating-gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing floating-gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple floating-gate MOS devices show various competitive and cooperative behaviors between devices. These floating-gate circuits can be used to build silicon systems that adapt and learn
Citation:
Paul Hasler, Bradley A. Minch, Chris Diorio, "Adaptive Circuits Using pFET Floating-Gate Devices," arvlsi, pp.215, 20th Anniversary Conference on Advanced Research in VLSI, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||