20th Anniversary Conference on Advanced Research in VLSI Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines Atlanta, Georgia March 21-March 24 ISBN: 0-7695-0056-0
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing ``time borrowing,'' i.e., allowing input signals to arrive at a pipe stage after the clock tick. We show a robust way of placing ``roadblocks'' (equivalent to slave latches) in each pipe stage to maintain the optimal clock rate. As explicit latches are not required at the pipe stage boundaries, the latch overhead is eliminated. We use the self-resetting scheme to circumvent often performance-limiting precharge timing requirements. We also address several issues regarding the testability of self-resetting domino circuits including scan register design and multiple stuck fault testing.
Index Terms:
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
Citation:
Ayoob E. Dooply, Kenneth Y. Yun, "Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines," arvlsi, pp.200, 20th Anniversary Conference on Advanced Research in VLSI, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||