One recent approach for power reduction is to employ different supply voltages for different parts of a design. This paper presents optimization methods that promote the use of dual supply voltages for power-driven designs. We first propose an iterative gate sizing and voltage scaling paradigm that progressively scales down the supply voltage under fixed timing constraint. Then, we propose a new physical layout style that supports dual supply voltages for cell-based designs. The new layout style can be automatically generated via a simulated annealing based placement algorithm. Experimental results using the MCNC benchmark circuits show that the proposed techniques produce very encouraging results.