Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic, high-capacitance nodes are adiabatically switched and powered from ac sources, typically the clock lines. Low-capacitance nodes are conventionally switched and powered from a dc supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the dc-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.