We present a novel architecture for column-based image processing within an integrated CMOS sensor chip. The system includes a two-dimensional array of active pixel sensors, a one-dimensional array of analog-to-digital converters along one side of the sensor array, an array of static random access memory (SRAM) cells, and a one- dimensional array of parallel digital processing units. The architecture offers much potential for scalability, primarily due to a rotation of the digital bits coming out of the analog-to-digital converter. Each data converter produces an 8-bit value, which is then stored horizontally in an SRAM byte extending across 8 columns of pixels. This arrangement of data enables 8-bit parallel processing by each of the arithmetic logic units (ALUs), which also extends along 8 pixel columns. This grouping of 8 columns is referred to as a block-column. We describe the architecture and discuss implementation issues encountered during the design of two separate test devices fabricated in a 0.35um digital CMOS process. We also present results of an architectural analysis with example algorithms.