17th Conference on Advanced Research in VLSI (ARVLSI '97)
Fault Scanner for Reconfigurable Logic
Ann Arbor, MI
September 15-September 16
ISBN: 0-8186-7913-1
Nathan R. Shnidman, Electrical Engineering Department, University of California, Los Angeles
Miodrag Potkonjak, Computer Science Department, University of California, Los Angeles
We propose a technique for online built-in self-test of Field Programmable Gate Arrays (FPGAs). The goal of this system is to detect deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. A system that solves these problems would be useful for mission-critical applications with resource constraints. We present here a fault detection system which solves these problems through an online fault scanning methodology. Resources internal to the device are configured to test for faults. Testing scans across an FPGA, checking a section at a time. The viability and effectiveness of such a system is supported through simulation of the system on a model FPGA.
Citation:
Nathan R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak, "Fault Scanner for Reconfigurable Logic," arvlsi, pp.238, 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997