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17th Conference on Advanced Research in VLSI (ARVLSI '97)
The Design of an Asynchronous MIPS R3000 Microprocessor
Ann Arbor, MI
September 15-September 16
ISBN: 0-8186-7913-1
ASCII Text
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Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nystroem, Paul Penzes, Robert Southworth, Uri Cummings, "The Design of an Asynchronous MIPS R3000 Microprocessor," Advanced Research in VLSI, Conference on, pp. 164, 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997.
 
 
BibTex
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@article{ 10.1109/ARVLSI.1997.634853,
author = {Alain J. Martin and Andrew Lines and Rajit Manohar and Mika Nystroem and Paul Penzes and Robert Southworth and Uri Cummings},
title = {The Design of an Asynchronous MIPS R3000 Microprocessor},
journal ={Advanced Research in VLSI, Conference on},
volume = {0},
year = {1997},
isbn = {0-8186-7913-1},
pages = {164},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1997.634853},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Advanced Research in VLSI, Conference on
TI - The Design of an Asynchronous MIPS R3000 Microprocessor
SN - 0-8186-7913-1
SP
EP
A1 - Alain J. Martin,
A1 - Andrew Lines,
A1 - Rajit Manohar,
A1 - Mika Nystroem,
A1 - Paul Penzes,
A1 - Robert Southworth,
A1 - Uri Cummings,
PY - 1997
VL - 0
JA - Advanced Research in VLSI, Conference on
ER -
 
Alain J. Martin, Department of Computer Science, California Institute of Technology
Andrew Lines, Department of Computer Science, California Institute of Technology
Rajit Manohar, Department of Computer Science, California Institute of Technology
Mika Nystroem, Department of Computer Science, California Institute of Technology
Paul Penzes, Department of Computer Science, California Institute of Technology
Robert Southworth, Department of Computer Science, California Institute of Technology
Uri Cummings, Department of Computer Science, California Institute of Technology
The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 micron CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 Watts. The paper describes the structure of a high- performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high frequency.
Citation:
Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nystroem, Paul Penzes, Robert Southworth, Uri Cummings, "The Design of an Asynchronous MIPS R3000 Microprocessor," arvlsi, pp.164, 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
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