An evaluation of bipartitioning techniques

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16th Conference on Advanced Research in VLSI (ARVLSI'95)

Chapel Hill, North Carolina

March 27-March 29

ISBN: 0-8186-7047-9

	ASCII Text	x
	S. Hauck, G. Borriello, "An evaluation of bipartitioning techniques," Advanced Research in VLSI, Conference on, pp. 383, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/ARVLSI.1995.515634, author = {S. Hauck and G. Borriello}, title = {An evaluation of bipartitioning techniques}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-7047-9}, pages = {383}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515634}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Research in VLSI, Conference on TI - An evaluation of bipartitioning techniques SN - 0-8186-7047-9 SP EP A1 - S. Hauck, A1 - G. Borriello, PY - 1995 KW - logic partitioning; logic CAD; circuit CAD; VLSI; integrated circuit design; bipartitioning techniques; logic partitioning; VLSI CAD VL - 0 JA - Advanced Research in VLSI, Conference on ER -

S. Hauck, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

G. Borriello, Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515634

Logic partitioning is an important issue in VLSI CAD, and has been an active area of research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a methodology for determining the best mix of approaches. The result is a novel bipartitioning algorithm that includes both new and pre-existing techniques. Our algorithm produces results that are at least 17% better than the state-of-the-art while also being efficient in run time.

Index Terms:

logic partitioning; logic CAD; circuit CAD; VLSI; integrated circuit design; bipartitioning techniques; logic partitioning; VLSI CAD

Citation:

S. Hauck, G. Borriello, "An evaluation of bipartitioning techniques," arvlsi, pp.383, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995

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