The polynomial-time retiming algorithms that were developed in the eighties assumed simple delay models that neglected several timing issues that arise in logic design. Recent retiming algorithms for more comprehensive delay models rely on non-linear formulations and run in worst-case exponential time using branch-and-bound techniques. In this paper, we investigate the retiming problem for edge-triggered circuits under a general delay model that handles load-dependent gate delays, register delays, interconnect delays, and clock skew. We show that in this model the retiming problem can be expressed as a set of integer linear programming constraints that can be solved using general ILP techniques. For the special case where clock skew is monotonic and all registers have equal propagation delays, we give an integer phonotonic programming formulation of the retiming problem, and we present an efficient algorithm for solving it. Our algorithm retimes any given edge-triggered circuit to achieve a specified clock period in O(V/sup 3/F) steps, where V is the number of logic gales in the circuit and F is bounded by the number of registers in the circuit. A straightforward extension of our algorithm determines a minimum clock period retiming in O(V/sup 3/Flg V) steps.