Low-latency plesiochronous data retiming

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	Similar Articles Articles by L.R. Dennison Articles by W.J. Dally Articles by D. Xanthopoulos

16th Conference on Advanced Research in VLSI (ARVLSI'95)

Chapel Hill, North Carolina

March 27-March 29

ISBN: 0-8186-7047-9

	ASCII Text	x
	L.R. Dennison, W.J. Dally, D. Xanthopoulos, "Low-latency plesiochronous data retiming," Advanced Research in VLSI, Conference on, pp. 304, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/ARVLSI.1995.515628, author = {L.R. Dennison and W.J. Dally and D. Xanthopoulos}, title = {Low-latency plesiochronous data retiming}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-7047-9}, pages = {304}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515628}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Research in VLSI, Conference on TI - Low-latency plesiochronous data retiming SN - 0-8186-7047-9 SP EP A1 - L.R. Dennison, A1 - W.J. Dally, A1 - D. Xanthopoulos, PY - 1995 KW - timing; telecommunication network routing; repeaters; telecommunication signalling; data retiming; plesiochronous data; latency; support circuitry; undirectional signalling; communication networks; repeaters; hubs; bridges; routers VL - 0 JA - Advanced Research in VLSI, Conference on ER -

L.R. Dennison, Artificial Intelligence Lab., MIT, Cambridge, MA, USA

W.J. Dally, Artificial Intelligence Lab., MIT, Cambridge, MA, USA

D. Xanthopoulos, Artificial Intelligence Lab., MIT, Cambridge, MA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515628

A new method of retiming plesiochronous data is described. This method features latency of less than a cell-time and requires only minimal support circuitry. No flow control or handshaking signals are used, allowing true undirectional signalling between transmitter and receiver. Application areas include communication networks in parallel computers, and general communication network repeaters, hubs, bridges, and routers.

Index Terms:

timing; telecommunication network routing; repeaters; telecommunication signalling; data retiming; plesiochronous data; latency; support circuitry; undirectional signalling; communication networks; repeaters; hubs; bridges; routers

Citation:

L.R. Dennison, W.J. Dally, D. Xanthopoulos, "Low-latency plesiochronous data retiming," arvlsi, pp.304, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995

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