Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics

A
ARVLSI
1995
16th Conference on Advanced Research in VLSI (ARVLSI'95)
Abstract - Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics

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16th Conference on Advanced Research in VLSI (ARVLSI'95)

Chapel Hill, North Carolina

March 27-March 29

ISBN: 0-8186-7047-9

	ASCII Text	x
	X. Cai, K. Nabors, J. White, "Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics," Advanced Research in VLSI, Conference on, pp. 200, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/ARVLSI.1995.515621, author = {X. Cai and K. Nabors and J. White}, title = {Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-7047-9}, pages = {200}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515621}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Research in VLSI, Conference on TI - Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics SN - 0-8186-7047-9 SP EP A1 - X. Cai, A1 - K. Nabors, A1 - J. White, PY - 1995 KW - Galerkin method; capacitance; boundary-elements methods; piecewise constant techniques; integrated circuit interconnections; VLSI; permittivity; circuit CAD; integrated circuit design; Galerkin techniques; multipole-accelerated capacitance extraction; 3D structures; multiple dielectrics; boundary element method; capacitance extraction; arbitrary piecewise-constant dielectric medium; IC interconnections; VLSI VL - 0 JA - Advanced Research in VLSI, Conference on ER -

X. Cai, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

K. Nabors, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

J. White, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515621

This paper describes an efficient implementation of a Galerkin based multipole-accelerated boundary element method for 3-D capacitance extraction of conductors in an arbitrary piecewise-constant dielectric medium. Results are presented to demonstrate that the Galerkin method is substantially more accurate than the commonly used collocation scheme for problems with dielectric interfaces. In addition, it is shown experimentally that for a given discretization, a careful implementation of the Galerkin method in a multipole-accelerated program is only slightly more computationally expensive than the collocation method.

Index Terms:

Galerkin method; capacitance; boundary-elements methods; piecewise constant techniques; integrated circuit interconnections; VLSI; permittivity; circuit CAD; integrated circuit design; Galerkin techniques; multipole-accelerated capacitance extraction; 3D structures; multiple dielectrics; boundary element method; capacitance extraction; arbitrary piecewise-constant dielectric medium; IC interconnections; VLSI

Citation:

X. Cai, K. Nabors, J. White, "Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics," arvlsi, pp.200, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995

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