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16th Conference on Advanced Research in VLSI (ARVLSI'95)
Recursive layout generation
Chapel Hill, North Carolina
March 27-March 29
ISBN: 0-8186-7047-9
ASCII Text
x 
 
L.M. Monier, R.W. Haddad, J. Dion, "Recursive layout generation," Advanced Research in VLSI, Conference on, pp. 172, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/ARVLSI.1995.515619,
author = {L.M. Monier and R.W. Haddad and J. Dion},
title = {Recursive layout generation},
journal ={Advanced Research in VLSI, Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-7047-9},
pages = {172},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515619},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Advanced Research in VLSI, Conference on
TI - Recursive layout generation
SN - 0-8186-7047-9
SP
EP
A1 - L.M. Monier,
A1 - R.W. Haddad,
A1 - J. Dion,
PY - 1995
KW - circuit layout CAD; VLSI; microprocessor chips; BiCMOS digital integrated circuits; logic CAD; recursive layout generation; VLSI chips; layout directives; netlist description; seamless integration; hand-drawn layout; synthesized layout; overall layout; dense VLSI; microprocessor chips
VL - 0
JA - Advanced Research in VLSI, Conference on
ER -
 
L.M. Monier, Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
R.W. Haddad, Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
J. Dion, Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
We present a recursive method for generating layout for VLSI chips based on integrating layout directives in the netlist description. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense BiCMOS VLSI microprocessor chips automatically.
Index Terms:
circuit layout CAD; VLSI; microprocessor chips; BiCMOS digital integrated circuits; logic CAD; recursive layout generation; VLSI chips; layout directives; netlist description; seamless integration; hand-drawn layout; synthesized layout; overall layout; dense VLSI; microprocessor chips
Citation:
L.M. Monier, R.W. Haddad, J. Dion, "Recursive layout generation," arvlsi, pp.172, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995
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