A fault-tolerant VLSI architecture implementing a bi-directional bit-serial A/D/A (analog-to-digital and digital-to-analog) converter is presented. Both functions of algorithmic D/A conversion and successive approximation A/D conversion are combined into a single device, converting bits in the order from most to least significant. The MSB-first order allows for robust implementation, relatively insensitive to component mismatches, offsets and nonlinearities. Also, since the A/D conversion makes use of the intermediate D/A conversion results, matched monotonic characteristics are obtained in both directions of conversion. The final D/A result is available at the end of A/D conversion, and can be used directly in applications calling for analog quantization. More general use of the A/D/A converter allows for bi-directional read/write digital access to local analog information in VLSI. The cell supports dense integration of low-power data conversion units along with digital processors or sensory circuitry in a standard CMOS process. Experimental results from a prototype VLSI implementation are included. Including control logic, the A/D/A cell measures 216 /spl mu/m/spl times/315 /spl mu/m in a 2 /spl mu/m CMOS process, and achieves 8-bit untrimmed monotonicity at 200 /spl mu/W power consumption for a 20 /spl mu/sec conversion cycle.