Abacus: a 1024 processor 8 ns SIMD array

A
ARVLSI
1995
16th Conference on Advanced Research in VLSI (ARVLSI'95)
Abstract - Abacus: a 1024 processor 8 ns SIMD array

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	Similar Articles Articles by M. Bolotski Articles by T. Simon Articles by C. Vieri Articles by R. Amirtharajah Articles by T.F. Knight, Jr.

16th Conference on Advanced Research in VLSI (ARVLSI'95)

Chapel Hill, North Carolina

March 27-March 29

ISBN: 0-8186-7047-9

	ASCII Text	x
	M. Bolotski, T. Simon, C. Vieri, R. Amirtharajah, T.F. Knight, Jr., "Abacus: a 1024 processor 8 ns SIMD array," Advanced Research in VLSI, Conference on, pp. 28, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/ARVLSI.1995.515609, author = {M. Bolotski and T. Simon and C. Vieri and R. Amirtharajah and T.F. Knight, Jr.}, title = {Abacus: a 1024 processor 8 ns SIMD array}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-7047-9}, pages = {28}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515609}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Research in VLSI, Conference on TI - Abacus: a 1024 processor 8 ns SIMD array SN - 0-8186-7047-9 SP EP A1 - M. Bolotski, A1 - T. Simon, A1 - C. Vieri, A1 - R. Amirtharajah, A1 - T.F. Knight, Jr., PY - 1995 KW - parallel architectures; reconfigurable architectures; VLSI; real-time systems; computer vision; bit-slice computers; Abacus; SIMD array; microarchitecture; reconfigurable bit-parallel array; communication primitives; VLSI implementation; system-level design issues; real-time early vision processing; bit-slice processing element; 8 ns VL - 0 JA - Advanced Research in VLSI, Conference on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.515609

Describes the Abacus machine at a number of levels. Presents the microarchitecture of the PE comprising the reconfigurable bit-parallel array, a set of arithmetic and communication primitives, details of the VLSI implementation, and system-level design issues of a high-speed SIMD array. The most concrete goal of the Abacus project was to design and build a machine that could be used by members of the MIT Artificial Intelligence Laboratory for real-time early vision processing. Along the way, we explored several architectural ideas.

Index Terms:

parallel architectures; reconfigurable architectures; VLSI; real-time systems; computer vision; bit-slice computers; Abacus; SIMD array; microarchitecture; reconfigurable bit-parallel array; communication primitives; VLSI implementation; system-level design issues; real-time early vision processing; bit-slice processing element; 8 ns

Citation:

M. Bolotski, T. Simon, C. Vieri, R. Amirtharajah, T.F. Knight, Jr., "Abacus: a 1024 processor 8 ns SIMD array," arvlsi, pp.28, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995

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