The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higher-order and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of medium-precision special-purpose applications. The Complex LNS (CLNS) is a generalization of LNS which represents complex values in log-polar form. CLNS is a more compact representation than traditional rectangular methods, reducing the cost of busses and memory in intensive complex-number applications like the FFT; however, prior CLNS implementations were either slow CORDIC-based or expensive 2D-table-based approaches. This paper attempts to leverage the recent advances made in real-valued LNS units for the more specialized context of CLNS. This paper proposes a novel approach to reduce the cost of CLNS addition by re-using a conventional real-valued LNS ALU with specialized CLNS hardware that is smaller than the real-valued LNS ALU to which it is attached. The resulting ALU is much less expensive than prior fast CLNS units at the cost of some extra delay. The extra hardware added to the ALU is for trigonometric-related functions, and may be useful in LNS applications other than CLNS. The novel algorithm proposed here is implemented using the FloPoCo library (which incorporates recent HOTBM advances in function-unit generation), and FPGA synthesis results are reported.