2009 19th IEEE Symposium on Computer Arithmetic A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor Portland, Oregon, USA June 08-June 10 ISBN: 978-0-7695-3670-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2009.19
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest.The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy.Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8.
Index Terms:
binary floating-point division, correct rounding, polynomial evaluation, code generation and validation, VLIW integer processor
Citation:
Claude-Pierre Jeannerod, Herve Knochel, Christophe Monat, Guillaume Revy, Gilles Villard, "A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor," arith, pp.95-103, 2009 19th IEEE Symposium on Computer Arithmetic, 2009 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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