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18th IEEE Symposium on Computer Arithmetic (ARITH '07)
Optimistic Parallelization of Floating-Point Accumulation
Montpellier, France
June 25-June 27
ISBN: 0-7695-2854-6
Nachiket Kapre, California Institute of Technology
Andre DeHon, University of Pennsylvania
Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the available precision. The resulting cyclic dependency in floating-point accumulation inhibits parallelization of the computation, including efficient use of pipelining. In practice, however, we observe that floating-point operations are "mostly" associative. This observation can be exploited to parallelize floating-point accumulation using a form of optimistic concurrency. In this scheme, we first compute an optimistic associative approximation to the sum and then relax the computation by iteratively propagating errors until the correct sum is obtained. We map this computation to a network of 16 statically-scheduled, pipelined, double-precision floating-point adders on the Virtex-4 LX160 (-12) device where each floating-point adder runs at 296MHz and has a pipeline depth of 10. On this 16 PE design, we demonstrate an average speedup of 6? with randomly generated data and 3-7? with summations extracted from Conjugate Gradient benchmarks.
Citation:
Nachiket Kapre, Andre DeHon, "Optimistic Parallelization of Floating-Point Accumulation," arith, pp.205-216, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007
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