18th IEEE Symposium on Computer Arithmetic (ARITH '07) Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell Montpellier, France June 25-June 27 ISBN: 0-7695-2854-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2007.15
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750MHz in 90nm CMOS. Logical Effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.
Citation:
Neil Burgess, Chris N. Hinds, "Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell," arith, pp.87-96, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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