17th IEEE Symposium on Computer Arithmetic (ARITH'05) An Improved Unified Scalable Radix-2 Montgomery Multiplier Cape Cod, Massachusetts, USA June 27-June 29 ISBN: 0-7695-2366-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2005.9
This paper describes an improved version of the Tenca-Ko? unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement. Like the Tenca-Ko? multiplier, this design is reconfigurable to accept any input precision in either GF(p) or GF(2ⁿ) up to the size of the on-chip memory. An FPGA implementation can perform 1024-bit modular exponentiation in 16 ms using 5598 4-input lookup tables, making it the fastest unified scalable design yet reported.
Citation:
David Harris, Ram Krishnamurthy, Mark Anders, Sanu Mathew, Steven Hsu, "An Improved Unified Scalable Radix-2 Montgomery Multiplier," arith, pp.172-178, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||