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17th IEEE Symposium on Computer Arithmetic (ARITH'05)
A Hardware Algorithm for Integer Division
Cape Cod, Massachusetts, USA
June 27-June 29
ISBN: 0-7695-2366-8
ASCII Text
x 
 
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi, "A Hardware Algorithm for Integer Division," Computer Arithmetic, IEEE Symposium on, pp. 140-146, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), 2005.
 
 
BibTex
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@article{ 10.1109/ARITH.2005.6,
author = {Naofumi Takagi and Shunsuke Kadowaki and Kazuyoshi Takagi},
title = {A Hardware Algorithm for Integer Division},
journal ={Computer Arithmetic, IEEE Symposium on},
volume = {0},
year = {2005},
issn = {1063-6889},
pages = {140-146},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2005.6},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Arithmetic, IEEE Symposium on
TI - A Hardware Algorithm for Integer Division
SN - 1063-6889
SP140
EP146
A1 - Naofumi Takagi,
A1 - Shunsuke Kadowaki,
A1 - Kazuyoshi Takagi,
PY - 2005
KW - null
VL - 0
JA - Computer Arithmetic, IEEE Symposium on
ER -
 
Naofumi Takagi, Nagoya University
Shunsuke Kadowaki, Nagoya University
Kazuyoshi Takagi, Nagoya University
A hardware algorithm for integer division is proposed. It is based on the digit-recurrence, non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. The algorithm does not require normalization of the divisor, and hence, does not require area-consuming leading one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, where pipelining is possible for increasing the throughput. Sequential implementation yields a compact divider.
Citation:
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi, "A Hardware Algorithm for Integer Division," arith, pp.140-146, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), 2005
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