Some Optimizations of Hardware Multiplication by Constant Matrices

A
ARITH
2003
16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03)
Abstract - Some Optimizations of Hardware Multiplication by Constant Matrices

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	Similar Articles Articles by Nicolas Boullis Articles by Arnaud Tisserand

16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03)

Santiago de Compostela, Spain

June 15-June 18

ISBN: 0-7695-1894-X

	ASCII Text	x
	Nicolas Boullis, Arnaud Tisserand, "Some Optimizations of Hardware Multiplication by Constant Matrices," Computer Arithmetic, IEEE Symposium on, pp. 20, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003.

	BibTex	x
	@article{ 10.1109/ARITH.2003.1207656, author = {Nicolas Boullis and Arnaud Tisserand}, title = {Some Optimizations of Hardware Multiplication by Constant Matrices}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {2003}, issn = {1063-6889}, pages = {20}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.1207656}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - Some Optimizations of Hardware Multiplication by Constant Matrices SN - 1063-6889 SP EP A1 - Nicolas Boullis, A1 - Arnaud Tisserand, PY - 2003 KW - null VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER -

Nicolas Boullis, École Normale Supérieure de Lyon

Arnaud Tisserand, École Normale Supérieure de Lyon

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.1207656

This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.

Citation:

Nicolas Boullis, Arnaud Tisserand, "Some Optimizations of Hardware Multiplication by Constant Matrices," arith, pp.20, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003

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