A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension

A
ARITH
1999
14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99)
Abstract - A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension

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	Similar Articles Articles by M.S. Schmookler Articles by M. Putrino Articles by A. Mather Articles by J. Tyler Articles by H.V. Nguyen Articles by C. Roth Articles by M. Sharma Articles by M.N. Pham Articles by J. Lent

14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99)

Adelaide, Australia

April 14-April 16

ISBN: 0-7695-0116-8

	ASCII Text	x
	M.S. Schmookler, M. Putrino, A. Mather, J. Tyler, H.V. Nguyen, C. Roth, M. Sharma, M.N. Pham, J. Lent, "A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension," Computer Arithmetic, IEEE Symposium on, pp. 12, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99), 1999.

	BibTex	x
	@article{ 10.1109/ARITH.1999.762823, author = {M.S. Schmookler and M. Putrino and A. Mather and J. Tyler and H.V. Nguyen and C. Roth and M. Sharma and M.N. Pham and J. Lent}, title = {A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {1999}, issn = {1063-6889}, pages = {12}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.1999.762823}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension SN - 1063-6889 SP EP A1 - M.S. Schmookler, A1 - M. Putrino, A1 - A. Mather, A1 - J. Tyler, A1 - H.V. Nguyen, A1 - C. Roth, A1 - M. Sharma, A1 - M.N. Pham, A1 - J. Lent, PY - 1999 VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER -

C. Roth

J. Lent

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.1999.762823

The AltiVec((tm)) technology is an extension to the PowerPC architecture((tm)) which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low cost, low power processor based on the acclaimed PowerPC 750((tm)) microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

Citation:

M.S. Schmookler, M. Putrino, A. Mather, J. Tyler, H.V. Nguyen, C. Roth, M. Sharma, M.N. Pham, J. Lent, "A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension," arith, pp.12, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99), 1999

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