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1997 Advances in Parallel and Distributed Computing Conference (APDC '97)
Parallel Replacement Mechanism for MultiThread
Shanghai, CHINA
March 19-March 21
ISBN: 0-8186-7876-3
Guangzuo Cui, Harbin Institute of Technology
Mingzeng Hu, Harbin Institute of Technology
Xiaoming Li, Northeast Parallel Architecture Center
This paper presents a new rapid thread replacement mechanism which is important in multithread technology. Analysis to the memory system indicates that the memory utilization decreases with the increase of cache hit ratio. The parallelism between thread computation and thread replacement is found by analyzing their working processes. Based on these, we advance a rapid multithread replacement mechanism which overlaps the thread replacement with thread computation. More especially, with finite hardware contexts, this mechanism can play the same role of infinite contexts by tolerating the replacement overhead. By modifying the general thread switching model, we build the thread replacement model and evaluate this mechanism in theory and experiment methods. At last, we discuss the hardware implementation and put forward the problems to be resolved in the future.
Index Terms:
parallel architectures, thread replacement mechanism, multithread technology, memory utilization, cache hit ratio, finite hardware
Citation:
Guangzuo Cui, Mingzeng Hu, Xiaoming Li, "Parallel Replacement Mechanism for MultiThread," apdc, pp.338, 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997
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