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1997 Advances in Parallel and Distributed Computing Conference (APDC '97)
A Dual-Processors Multithreaded Architecture and Its Driven Execution Model
Shanghai, CHINA
March 19-March 21
ISBN: 0-8186-7876-3
ASCII Text
x 
 
Liquan Xiao, Weixia Xu, Xingming Zhou, "A Dual-Processors Multithreaded Architecture and Its Driven Execution Model," Advances in Parallel and Distributed Computing Conference, pp. 214, 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997.
 
 
BibTex
x
 
@article{ 10.1109/APDC.1997.574035,
author = {Liquan Xiao and Weixia Xu and Xingming Zhou},
title = {A Dual-Processors Multithreaded Architecture and Its Driven Execution Model},
journal ={Advances in Parallel and Distributed Computing Conference},
volume = {0},
year = {1997},
isbn = {0-8186-7876-3},
pages = {214},
doi = {http://doi.ieeecomputersociety.org/10.1109/APDC.1997.574035},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Advances in Parallel and Distributed Computing Conference
TI - A Dual-Processors Multithreaded Architecture and Its Driven Execution Model
SN - 0-8186-7876-3
SP
EP
A1 - Liquan Xiao,
A1 - Weixia Xu,
A1 - Xingming Zhou,
PY - 1997
KW - parallel architectures
KW - dual-processors multithreaded architecture
KW - driven execution model
KW - software overhead
KW - interprocess communication latency
KW - management processes
KW - performance
KW - massively parallel processors
KW - multiple threaded architecture
KW - microprocessors
KW - hardware description language
KW - trace driven simulator
VL - 0
JA - Advances in Parallel and Distributed Computing Conference
ER -
 
Liquan Xiao, Dept. of Comput., Changsha Inst. of Technol., China
Weixia Xu, Dept. of Comput., Changsha Inst. of Technol., China
Xingming Zhou, Dept. of Comput., Changsha Inst. of Technol., China
The software overhead which includes interprocess communication latency and the overhead of management processes or threads, is a crucial factor to affect the performance of massively parallel processors system. Multiple threaded architecture can effectively reduce and hide the software overhead. Many models need to be implemented inside a microprocessor. Conversely, this paper addresses a multiple threaded architecture adopted for current microprocessors and implements the architecture using hardware description language. Furthermore, the paper presents its driven execution model and evaluates the performance of the presented multithreading system using a trace driven simulator.
Index Terms:
parallel architectures, dual-processors multithreaded architecture, driven execution model, software overhead, interprocess communication latency, management processes, performance, massively parallel processors, multiple threaded architecture, microprocessors, hardware description language, trace driven simulator
Citation:
Liquan Xiao, Weixia Xu, Xingming Zhou, "A Dual-Processors Multithreaded Architecture and Its Driven Execution Model," apdc, pp.214, 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997
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