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2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95)
A Configurable Parallel Neurocomputer
Dunedin, New Zealand
November 20-November 23
ISBN: 0-8186-7174-2
ASCII Text
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Alfred Strey, Narcis Avellana, Raul Holgado, Ramon Capillas, J. Alberto Fernandez, Elena Valderrama, "A Configurable Parallel Neurocomputer," Artificial Neural Networks and Expert Systems, New Zealand Conference, pp. 55, 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), 1995.
 
 
BibTex
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@article{ 10.1109/ANNES.1995.499438,
author = {Alfred Strey and Narcis Avellana and Raul Holgado and Ramon Capillas and J. Alberto Fernandez and Elena Valderrama},
title = {A Configurable Parallel Neurocomputer},
journal ={Artificial Neural Networks and Expert Systems, New Zealand Conference},
volume = {0},
year = {1995},
isbn = {0-8186-7174-2},
pages = {55},
doi = {http://doi.ieeecomputersociety.org/10.1109/ANNES.1995.499438},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Artificial Neural Networks and Expert Systems, New Zealand Conference
TI - A Configurable Parallel Neurocomputer
SN - 0-8186-7174-2
SP
EP
A1 - Alfred Strey,
A1 - Narcis Avellana,
A1 - Raul Holgado,
A1 - Ramon Capillas,
A1 - J. Alberto Fernandez,
A1 - Elena Valderrama,
PY - 1995
KW - neural hardware
KW - neurocomputer
KW - parallel computer
VL - 0
JA - Artificial Neural Networks and Expert Systems, New Zealand Conference
ER -
 
Alfred Strey, Universitaet Ulm
Narcis Avellana, Universidad Autonoma de Barcelona - C.N.M.
Raul Holgado, Universidad Autonoma de Barcelona - C.N.M.
Ramon Capillas, Universidad Autonoma de Barcelona - C.N.M.
J. Alberto Fernandez, Universidad Autonoma de Barcelona - C.N.M.
Elena Valderrama, Universidad Autonoma de Barcelona - C.N.M.
This paper presents the architecture of a new configurable parallel neurocomputer optimized for the high-speed simulation of neural networks. Its main system feature is the reconfigurability of a new arithmetical unit chip which supports several accuracies in all typical neural network operations. If the required accuracy is decreased the degree of parallelism inside the chip can be increased by a dynamical reconfiguration of the hardware resources. The system also offers a good scalability: for the simulation of large neural networks the system performance can easily be increased by using several arithmetical unit chips operating in parallel.
Index Terms:
neural hardware, neurocomputer, parallel computer
Citation:
Alfred Strey, Narcis Avellana, Raul Holgado, Ramon Capillas, J. Alberto Fernandez, Elena Valderrama, "A Configurable Parallel Neurocomputer," annes, pp.55, 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), 1995
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