loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95)
An area efficient implementation of a cellular neural network
Dunedin, New Zealand
November 20-November 23
ISBN: 0-8186-7174-2
ASCII Text
x 
 
K.K. Lai, P.H.W. Leong, "An area efficient implementation of a cellular neural network," Artificial Neural Networks and Expert Systems, New Zealand Conference, pp. 51, 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/ANNES.1995.499437,
author = {K.K. Lai and P.H.W. Leong},
title = {An area efficient implementation of a cellular neural network},
journal ={Artificial Neural Networks and Expert Systems, New Zealand Conference},
volume = {0},
year = {1995},
isbn = {0-8186-7174-2},
pages = {51},
doi = {http://doi.ieeecomputersociety.org/10.1109/ANNES.1995.499437},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Artificial Neural Networks and Expert Systems, New Zealand Conference
TI - An area efficient implementation of a cellular neural network
SN - 0-8186-7174-2
SP
EP
A1 - K.K. Lai,
A1 - P.H.W. Leong,
PY - 1995
KW - cellular neural nets; neural chips; VLSI; cellular logic; circuit analysis computing; edge detection; cellular neural network; area efficient implementation; time multiplexing scheme; higher density implementations; VLSI circuits; simulation; neural circuits; edge detection
VL - 0
JA - Artificial Neural Networks and Expert Systems, New Zealand Conference
ER -
 
K.K. Lai, Dept. of Electr. Eng., Sydney Univ., NSW, Australia
P.H.W. Leong, Dept. of Electr. Eng., Sydney Univ., NSW, Australia
A time multiplexing scheme for implementing cellular neural networks (CNN) is described. This scheme makes it possible to realise much higher density implementations of CNNs in VLSI circuits. A circuit implementation of this technique is presented along with simulation results.
Index Terms:
cellular neural nets; neural chips; VLSI; cellular logic; circuit analysis computing; edge detection; cellular neural network; area efficient implementation; time multiplexing scheme; higher density implementations; VLSI circuits; simulation; neural circuits; edge detection
Citation:
K.K. Lai, P.H.W. Leong, "An area efficient implementation of a cellular neural network," annes, pp.51, 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), 1995
Usage of this product signifies your acceptance of the Terms of Use.