Two lifting-based VLSI architectures for 2-DDWT for lossless 5/3 and lossy 9/7 algorithms were proposedby Ibrahim et al., based on two scan methods, overlapped and nonoverlaped. In the architecture based on the overlapped scan method, the maximum power consumption occurs due to overlap external frame memory access. On the other hand, in the nonoverlapped architecture, the power consumption was reduced to minimum by eliminating the overlapped areas which requires the addition of a line buffer of size N. Furthermore, the performance evaluations by Ibrahim el at., show that those pipelined architectures are optimal in terms of speedup, efficiency and hardware utilization. In this paper, we proposed new architecture, called intermediate architecture, for both 5/3 and 9/7algorithms, which aim at reducing the power consumption of the overlapped areas, without using the expensive linebuffer, to somewhat between the two extreme architectures proposed by Ibrahim et al.