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21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07)
An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar
Niagara Falls, Ontario, Canada
May 21-May 23
ISBN: 0-7695-2847-3
Rongrong Zhong, Shanghai Jiao Tong University, China
Yongxin Zhu, Shanghai Jiao Tong University, China
Weiwei Chen, Shanghai Jiao Tong University, China
Mingliang Lin, Shanghai Jiao Tong University, China
Weng-Fai Wong, National University of Singapore, Singapore
In the recent years, multi-core processors prove their extensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among different processing modules. A shared memory scheme is introduced for inter-core communication with a set of shared memory access instructions and communicationmethods. A synchronization mechanism, which only switches the simulation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms.
Citation:
Rongrong Zhong, Yongxin Zhu, Weiwei Chen, Mingliang Lin, Weng-Fai Wong, "An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar," ainaw, vol. 1, pp.758-763, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), 2007
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