21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07) Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2^m) Niagara Falls, Ontario, Canada May 21-May 23 ISBN: 0-7695-2847-3
Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents a unified systolic multiplier under the method of the multiply-by-\alpha^2 and the folded technique. This circuit can be suited for implementing both multiplication and squaring in GF(2^m). The results show that our proposed multiplier saves about 75% space complexity and 50% latency as compared to the traditional multipliers proposed by Yeh et al. and Wang-Lin. Also, the proposed squarer saves about 45% space complexity as compared to the traditional squarer presented by Guo and Wang.
Citation:
Chiou-Yng Lee, Yung-Hui Chen, "Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2^m)," ainaw, vol. 1, pp.906-911, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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