2009 International Conference on Advanced Information Networking and Applications Quarc: A High-Efficiency Network on-Chip Architecture Bradford, United Kingdom May 26-May 29 ISBN: 978-0-7695-3638-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AINA.2009.64
Th novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC. This paper provides an ASIC implementation of both architectures using UMC’s 0:13um CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs.
Index Terms:
Quarc, Network On Chip, ASIC
Citation:
Mahmoud Moadeli, Partha Maji, Wim Vanderbauwhede, "Quarc: A High-Efficiency Network on-Chip Architecture," aina, pp.98-105, 2009 International Conference on Advanced Information Networking and Applications, 2009 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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