22nd International Conference on Advanced Information Networking and Applications (aina 2008) Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors March 25-March 28 ISBN: 978-0-7695-3095-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AINA.2008.50
This work tries to derive ideas for thread allocation in Chip Multiprocessor (CMP)-based network processors performing general applications by Continuous-Time Markov Chain modeling and Petri net simulations. The concept of P-M ratio, where P and M indicate the computational and memory access overhead when processing a packet, is introduced and the relation to thread allocation is explored. Results indicate that the demand of threads in a processor diminishes rapidly as P-M ratio increases to 0.066, and decreases slowly afterwards. Observations from a certain P-M ratio can be applied to various software-hardware combinations having the same ratio.
Index Terms:
thread allocation, chip multiprocessor, modeling, Petri net, simulation
Citation:
Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai, "Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors," aina, pp.718-725, 22nd International Conference on Advanced Information Networking and Applications (aina 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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