Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05) The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets Lisbon, Portugal July 17-July 22 ISBN: 0-7695-2388-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AICT.2005.88
In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbps using standard FPGA technology.
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Citation:
Stephen O?Kane, Colm McKillen, Sakir Sezer, "The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets," aict-sapir-elete, pp.352-356, Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||