A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA

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	Similar Articles Articles by Ciaran Toal Articles by Sakir Sezer

Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05)

Lisbon, Portugal

July 17-July 22

ISBN: 0-7695-2388-9

	ASCII Text	x
	Ciaran Toal, Sakir Sezer, "A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA," Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop, pp. 357-362, Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05), 2005.

	BibTex	x
	@article{ 10.1109/AICT.2005.1, author = {Ciaran Toal and Sakir Sezer}, title = {A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA}, journal ={Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop}, volume = {0}, year = {2005}, isbn = {0-7695-2388-9}, pages = {357-362}, doi = {http://doi.ieeecomputersociety.org/10.1109/AICT.2005.1}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop TI - A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA SN - 0-7695-2388-9 SP357 EP362 A1 - Ciaran Toal, A1 - Sakir Sezer, PY - 2005 KW - reg VL - 0 JA - Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop ER -

Ciaran Toal, Queen?s University Belfast

Sakir Sezer, Queen?s University Belfast

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AICT.2005.1

This paper presents the design and study of an architecture able to perform 10Gbps GFP frame delineation with single bit error correction on an FPGA. The design targets the development of a System-On-Chip (SoC) platform for the design of next generation network processing. In order to achieve the high processing rate, the circuit is designed with a 64-bit data-path and is targeted to Altera Stratix II FPGA technology. The circuit operates at a clock rate of 165 MHz. The circuit utilises 8 parallel CRC HEC calculators and comparators, a PLI frame counter and a single bit error correction mechanism.

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Citation:

Ciaran Toal, Sakir Sezer, "A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA," aict-sapir-elete, pp.357-362, Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05), 2005

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