loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ACS/IEEE 2005 International Conference on Computer Systems and Applications (AICCSA'05)
Acyclic circuit partitioning for path delay fault emulation
Cairo, Egypt
January 03-January 06
ISBN: 0-7803-8735-X
F. Kocan, Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
M.H. Gunes, Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Summary form only given. Acyclic partitioning of VLSI circuits is studied under area/delay, 1-0 size and communication constraints. In this paper, we define the path-delay-fault emulation problem which adds a new constraint, viz. path count constraint, to partitioning problem. We present two algorithms to solve the problem. The first algorithm decomposes a circuit into entirely-fanout-free cones (EFFC), and clusters them into partitions. The second one finds an intermediate partitioning solution with the partitioning algorithm ignoring path count constraint. Later, it applies the first algorithm to the partitions which violate the path count constraint. We implemented the first algorithm and measured its efficiency in terms of the number of resulting partitions, cut-cost, and time cost for ISCAS85 benchmarks.
Citation:
F. Kocan, M.H. Gunes, "Acyclic circuit partitioning for path delay fault emulation," aiccsa, pp.22-I, ACS/IEEE 2005 International Conference on Computer Systems and Applications (AICCSA'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.