Novel Content Addressable Memory Architecture for Adaptive Systems

A
AHS
2007
Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
Abstract - Novel Content Addressable Memory Architecture for Adaptive Systems

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Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

University of Edinburgh, Scotland, United Kingdom

August 05-August 08

ISBN: 0-7695-2866-X

	ASCII Text	x
	Xin Yang, Sakir Sezer, John McCanny, Dwayne Burns, "Novel Content Addressable Memory Architecture for Adaptive Systems," Adaptive Hardware and Systems, NASA/ESA Conference on, pp. 633-640, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.

	BibTex	x
	@article{ 10.1109/AHS.2007.79, author = {Xin Yang and Sakir Sezer and John McCanny and Dwayne Burns}, title = {Novel Content Addressable Memory Architecture for Adaptive Systems}, journal ={Adaptive Hardware and Systems, NASA/ESA Conference on}, volume = {0}, year = {2007}, isbn = {0-7695-2866-X}, pages = {633-640}, doi = {http://doi.ieeecomputersociety.org/10.1109/AHS.2007.79}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Adaptive Hardware and Systems, NASA/ESA Conference on TI - Novel Content Addressable Memory Architecture for Adaptive Systems SN - 0-7695-2866-X SP633 EP640 A1 - Xin Yang, A1 - Sakir Sezer, A1 - John McCanny, A1 - Dwayne Burns, PY - 2007 KW - null VL - 0 JA - Adaptive Hardware and Systems, NASA/ESA Conference on ER -

Xin Yang, Queen?s University Belfast, Northern Ireland,United Kingdom

Sakir Sezer, Queen?s University Belfast, Northern Ireland,United Kingdom

John McCanny, Queen?s University Belfast, Northern Ireland,United Kingdom

Dwayne Burns, Queen?s University Belfast, Northern Ireland,United Kingdom

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AHS.2007.79

Content Addressable Memory (CAM) is an essential component of high-end network processing systems. In this paper, a novel CAM cell is presented. By simply setting the control signal onto the cell, it can be configured as either the binary or ternary CAM. Simulations on a 64-bit CAM test circuit using 0.13?m process have been carried out. The functionality, timing and power performance of proposed CAM array are discussed.

Citation:

Xin Yang, Sakir Sezer, John McCanny, Dwayne Burns, "Novel Content Addressable Memory Architecture for Adaptive Systems," ahs, pp.633-640, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

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