Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptation of CAD design tool is essential for the development of these arrays. While the performance of conventional FPGAs is limited by their predefined architecture, domainspecific reconfigurable arrays target a set of similar applications and their architectures can be tailored to maximize performance within the domain. This paper describes the placement problem for such arrays. It reviews the difficulties encountered implementing genetic algorithm based placement in a previous attempt and presents a hybrid approach by combining genetic algorithm and simulated annealing. The placement algorithm took account of wirelength, pin locations of each block and aims to minimise the total routing resource of the target circuits. It was successfully tested against two set of domain-specific architectures implementing DCT and Algebraic Codebook Search. Its performance was also accessed against five large benchmark circuits in the literature and the results shows significant improvement over the previous approach.