An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

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	Similar Articles Articles by Ciaran Toal Articles by Dwayne Burns Articles by Kieran McLaughlin Articles by Sakir Sezer Articles by Stephen O?Kane

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

University of Edinburgh, Scotland, United Kingdom

August 05-August 08

ISBN: 0-7695-2866-X

	ASCII Text	x
	Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O?Kane, "An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing," Adaptive Hardware and Systems, NASA/ESA Conference on, pp. 613-618, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.

	BibTex	x
	@article{ 10.1109/AHS.2007.30, author = {Ciaran Toal and Dwayne Burns and Kieran McLaughlin and Sakir Sezer and Stephen O?Kane}, title = {An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing}, journal ={Adaptive Hardware and Systems, NASA/ESA Conference on}, volume = {0}, year = {2007}, isbn = {0-7695-2866-X}, pages = {613-618}, doi = {http://doi.ieeecomputersociety.org/10.1109/AHS.2007.30}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Adaptive Hardware and Systems, NASA/ESA Conference on TI - An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing SN - 0-7695-2866-X SP613 EP618 A1 - Ciaran Toal, A1 - Dwayne Burns, A1 - Kieran McLaughlin, A1 - Sakir Sezer, A1 - Stephen O?Kane, PY - 2007 KW - null VL - 0 JA - Adaptive Hardware and Systems, NASA/ESA Conference on ER -

Ciaran Toal, Queen?s University Belfast

Dwayne Burns, Queen?s University Belfast

Kieran McLaughlin, Queen?s University Belfast

Sakir Sezer, Queen?s University Belfast

Stephen O?Kane, Queen?s University Belfast

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AHS.2007.30

This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a linked-list of the packet memory addresses which is maintained by the packet buffer controller. The architecture is pipelined and optimised to combat the latencies involved with RLDRAM II technologies to enable a high performance low cost packet buffer implementation.

Citation:

Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O?Kane, "An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing," ahs, pp.613-618, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

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