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Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
A Configurable IP for Mode Decision of H.264/AVC Encoder
University of Edinburgh, Scotland, United Kingdom
August 05-August 08
ISBN: 0-7695-2866-X
ASCII Text
x 
 
Shih-Chang Hsia, Si-Hong Wang, Ying- Chao Chou, "A Configurable IP for Mode Decision of H.264/AVC Encoder," Adaptive Hardware and Systems, NASA/ESA Conference on, pp. 146-152, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.
 
 
BibTex
x
 
@article{ 10.1109/AHS.2007.2,
author = {Shih-Chang Hsia and Si-Hong Wang and Ying- Chao Chou},
title = {A Configurable IP for Mode Decision of H.264/AVC Encoder},
journal ={Adaptive Hardware and Systems, NASA/ESA Conference on},
volume = {0},
year = {2007},
isbn = {0-7695-2866-X},
pages = {146-152},
doi = {http://doi.ieeecomputersociety.org/10.1109/AHS.2007.2},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Adaptive Hardware and Systems, NASA/ESA Conference on
TI - A Configurable IP for Mode Decision of H.264/AVC Encoder
SN - 0-7695-2866-X
SP146
EP152
A1 - Shih-Chang Hsia,
A1 - Si-Hong Wang,
A1 - Ying- Chao Chou,
PY - 2007
KW - null
VL - 0
JA - Adaptive Hardware and Systems, NASA/ESA Conference on
ER -
 
Shih-Chang Hsia, National Kaohsiung First University of Science and Technology, Taiwan
Si-Hong Wang, National Kaohsiung First University of Science and Technology, Taiwan
Ying- Chao Chou, National Kaohsiung First University of Science and Technology, Taiwan
In this paper, we present a configurable IP for the mode decision in intra predictor of H.264 system. The parallel architecture with three computational cores is proposed by using configurable structure to process YUV pixels, where the number of pixel parallelism is 10 in the output. A commonly hardware is used to computed various coding modes by arranging an efficient schedule for YUV Plane modes computing. The configurable circuit is controlled with multiplex to compute mode parameters to reduce the hardware cost. The luminance with 4x4 and 16x16 block mode and chrominance with 8x8 block mode can be finished during 256 cycles for one MB coding. The throughput rate is about 4~5 times compared to the previous works, and the proposed architecture can meet the speed requirement for 1920*1080/50Hz HDTV encoder.
Citation:
Shih-Chang Hsia, Si-Hong Wang, Ying- Chao Chou, "A Configurable IP for Mode Decision of H.264/AVC Encoder," ahs, pp.146-152, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
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