This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller components allow for better system adaptation, which is an expected feature of reconfigurable systems for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) according to CCSDS recommendations, and targeting an FPGA platform. The paper investigates traditional alternatives for the encoder implementation, introduces the algebraic theory behind the proposed approach, describes the design process and discusses the area figures reached by the new design.