Systolic Array Based Architecture for Variable Block-Size Motion Estimation

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	Similar Articles Articles by Liang Lu Articles by John V. McCanny Articles by Sakir Sezer

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

University of Edinburgh, Scotland, United Kingdom

August 05-August 08

ISBN: 0-7695-2866-X

	ASCII Text	x
	Liang Lu, John V. McCanny, Sakir Sezer, "Systolic Array Based Architecture for Variable Block-Size Motion Estimation," Adaptive Hardware and Systems, NASA/ESA Conference on, pp. 160-168, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.

	BibTex	x
	@article{ 10.1109/AHS.2007.103, author = {Liang Lu and John V. McCanny and Sakir Sezer}, title = {Systolic Array Based Architecture for Variable Block-Size Motion Estimation}, journal ={Adaptive Hardware and Systems, NASA/ESA Conference on}, volume = {0}, year = {2007}, isbn = {0-7695-2866-X}, pages = {160-168}, doi = {http://doi.ieeecomputersociety.org/10.1109/AHS.2007.103}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Adaptive Hardware and Systems, NASA/ESA Conference on TI - Systolic Array Based Architecture for Variable Block-Size Motion Estimation SN - 0-7695-2866-X SP160 EP168 A1 - Liang Lu, A1 - John V. McCanny, A1 - Sakir Sezer, PY - 2007 KW - null VL - 0 JA - Adaptive Hardware and Systems, NASA/ESA Conference on ER -

Liang Lu, Queen?s University of Belfast, Belfast, BT3 9DT, UK

John V. McCanny, Queen?s University of Belfast, Belfast, BT3 9DT, UK

Sakir Sezer, Queen?s University of Belfast, Belfast, BT3 9DT, UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/AHS.2007.103

A new Systolic Array based architecture is introduced for Variable block-size motion estimation (VBSME). This comprises a 2D array structure for SAD value computation combined with a parallel adder tree and a SAD comparator unit. Parallel raster scan is applied leading to high processor utilization. The exhibits much simpler control and lower hardware cost compared with previous circuits and can handle flexible search ranges without any increase in silicon area. Resulting computational rates are suitable for high end video processing applications. This architecture can also be simply configured as other video compression standards usage. Silicon design studies, based on a 0.13?m CMOS technology, indicate that circuits based on this approach are suitable for SDTV applications with search ranges of up to 32~32 and for HDTV applications with a search range of at least 16~16, with increased ranges achievable using lower dimension technologies.

Citation:

Liang Lu, John V. McCanny, Sakir Sezer, "Systolic Array Based Architecture for Variable Block-Size Motion Estimation," ahs, pp.160-168, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

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