Large multipliers are important for cryptographic applications because they need large keys. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, reconfigurability of multiplication is a difficult task, especially when bit-lengths are large, say over 500 bits. For fixed bit-lengths, much work has been done in the range of 32, 64 or even 128 bits for advanced microprocessors and DSPs. The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems. We present a multiplication scheme for higher radix multiplexer-based array multipliers and we suggest a parallelization of the scheme within a single FPGA based implementation. We also suggest a novel partition of the multiplier into folded pipeline stages such that each stage can be instantiated by reconfiguration from its preceding stage during the multiplication operation. The number of partition stages is flexible to meet the FPGA resource constraints. The rationale for pipeline folding is that the multiplier size may preclude a monolithic implementation within one FPGA chip. Using additional FPGAs reduces performance due to interchip communication. Results of large reconfigurable multipliers for 256-bits and over implemented in Xilinx Virtex4 are provided.