Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these heterogeneous arrays is a labour intensive process. Furthermore, the manual creation of the array architecture could not have been fully optimised, hence limiting their performance. This paper presents a placement technique for mapping logic elements into heterogeneous reconfigurable arrays. At its core, it implements a Genetic Algorithm, which was used to reduce the span of all the interconnections as well as critical delay. It therefore minimises the amount of routing resource required in the architecture. The algorithm was tested on two arrays implementing DCT and Speech Coding. The resulting architecture achieves optimal close to that of an expert designer in a fraction of the time.